With increases in speed of processing of processors, the reduction of time to access a memory has been demanded. One of the solutions for reduction of the time to access a memory may be a prefetch method for, before a processor issues an access request, predicting the address to be requested to access by the processor and holding the data at the address in a cache.
The prefetch method can detect a serial-access pattern when the processor executes a program to perform a memory access to serial addresses. However, detecting a serial-access pattern of accesses is difficult when the access order is reversed across a registration block boundary in a cache memory or when the access addresses are discrete. Under the above circumstances, a detection failure of the access pattern causes the registration of an undesirable access address by the prefetch, which is a problem.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2002-215456